1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device. More particularly, the present invention relates to a fabrication method of a gate junction conductive structure.
2. Description of the Related Art
When the density of an integrated circuit is further increased, the device dimensions such as the line width, the contact surface area and the junction depth are continuously being reduced to a deep submicron level. To effectively ensure the functional integrity of the device, to lower the resistance and to minimize the RC delay resulted from a reduced resistance and capacitance, a metal silicide is commonly used in the manufacturing of a gate for lowering the contact resistance of a polysilicon gate. Since the formation of a metal silicide eliminates the needs of a photolithography process, the process is also being referred as a self-aligned silicide (salicide) process. Common examples of a self-aligned silicide include titanium silicide (TiSi.sub.x) and cobalt silicide (CoSi.sub.x).
In the conventional self-aligned silicide process, using titanium silicide as an example, a transistor device and the device isolation region are first completed. The transistor comprises a polysilicon gate and a source/drain region. A layer of titanium is deposited on the entire substrate, and thermal treatment is then conducted to form a silicide layer. Silicide is formed at the elevated temperature where titanium is in contact and reacted with the silicon of the gate and the surface of the source/drain region. The unreacted metal is removed, leaving only the titanium silicide layer on the surface of the gate and the source/drain region. After that, an annealing procedure is conducted to enhance the quality of the titanium silicide layer.
As the dimensions of a polysilicon gate are gradually being reduced, a narrow line effect often occurs. A narrow line effect may result from too small a gate dimension, less than 0.18 .mu.m, such that the contact stress between the metal silicide and the polysilicon is too high during the formation of the metal silicide on the polysilicon gate. A narrow line effect may also result from too little a nucleation site, thereby reducing the quality of the metal silicide thin film, leading to an increase in the sheet resistance and affecting the operational efficiency of the gate.
To improve the quality of a metal silicide layer, a higher temperature by means of a rapid thermal processing (RTP) is used. A higher temperature, however, affects the characteristic of a shallow junction device. Furthermore, the issue of filament, which may lead to a shortage at the gate and at the source/drain region and resulted in a damage to the device, easily occurs between the gate and the source/drain region in the self-aligned silicide process.